Method of updating a shift register

ABSTRACT

There is disclosed a method of updating a pseudo noise code shift retiser in a noise code shift register in a software implemented CDMA system from a current value, including representing a tap polynomial as a tap polynomial binary sequence logically AND-ing the value of a last stage of the current value of the register with each of the bits of the tap polynomial sequence and logically XOR-ing the result of the logical AND operation with the current value of the register.

FIELD OF THE INVENTION

The present invention relates generally to cellular telecommunicationsand more specifically to a technique for updating a shift registerholding a pseudo-noise sequence. The technique may be used in connectionwith the generation of short codes and for long codes in a code divisionmultiple access (CDMA) communication system.

BACKGROUND TO THE INVENTION

CDMA systems and protocols are specified in Interim-Standard ninety-five(IS-95) by the US Telecommunications Industry Association and CDMA2000RC1.

The link between a mobile station and a base station is made up of twochannels, the forward channel (from the base station to the mobilestation) and the reverse channel (from the mobile station to the basestation).

The forward channel is composed of four different types of codechannels: a pilot channel, sync channel, paging channels and forwardtraffic channels.

A typical forward CDMA channel consists of 64 code channels. The 64 codechannels consist of a pilot channel, one sync channel, seven pagingchannels and 55 forward traffic channels.

The pilot channel is an unmodulated, direct-sequence spread spectrumsignal that is transmitted at all times by the base station on everyactive forward channel. The mobile station monitors the pilot channel toacquire the timing of the forward CDMA channel and to obtain a phasereference for coherent demodulation.

The sync channel is used to transport synchronisation messages to mobilestations within a CDMA cell. It is used by the mobile station to acquireinitial time synchronisation.

The paging channel is used to transmit control information and pages tomobile stations residing in the CDMA cell.

The forward traffic channel is used for transmission of user andsignalling traffic from the base station to a specific mobile stationduring a phone call.

All of the code channels in the forward CDMA channel are orthogonallyspread by an appropriate Walsh function and then undergo quadraturespreading (the sync channel, paging channel and forward traffic channelalso undergo several other processes before being orthogonally spread).

In particular, long codes which are pseudo-noise PN sequences, are usedto scramble the paging and traffic channels. Each channel is uniquelyassigned a long PN code which has a period of 2⁴²−1 chips. The long codeis specified by the characteristic polynomialp(x)=x⁴²+x³⁵+x³³+x³¹+x²⁷+x²⁶+x²⁵+x²²+x²¹+x⁺¹⁹+x¹⁸+x¹⁷+x¹⁶+x¹⁰+x⁷+x⁶+x⁵+x³+x²+x¹+1.Each PN chip of the long code is usually generated by inner product of a42 bit mask (a code exclusive to the channel) and the 42 bit statevector of a linear sequence generator.

In the prior art, a PN sequence is usually generated by a linear PN squence gen rator which consists of a 42 stage linear feedback shift rgister where the feedback logic is exclusive-OR (XOR) gates. Binarysequences are shifted through the shift registers in response to clockpulses, and the output of the various stages are logically combined andfed back as the input to the first stage. A 42-stage linear shiftregister generates a maximal length PN sequence of 2⁴²−1 symbols.

Further details of PN sequence generation can be found by reference toIS-95 or by referring to text books such as Wireless CommunicationsPrinciples & Practice by Theodore S. Rappaport (ISBN 0-13-375536-3).

It will be appreciated that in order to achieve the IS-95 PN sequencechip rate of 1.2288 million chips per second, the shift register must beupdated approximately every 19.5 microseconds. A single chip of the PNsequence must be produced approximately every 52 microseconds.

The forward CDMA channels are all orthogonally spread using WalshFunctions at a fixed chip rate of 1.2288 Mcps. The purpose of orthogonalspreading is to provide orthogonal channelization among all codechannels. The pilot channel is always spread with Walsh code 0, the SYNCchannel is always spread with Walsh code 32 and the paging channels areassigned Walsh codes 1 through 7.

Following Walsh spreading, all code channels undergo QuadratureSpreading, which involves performing the modulo-2 addition of theorthogonally spread data with the short code pseudo noise (PN) sequencegenerated by the short code generator. The tap polynomials for the ShortCode shift registers are:P _(I)(x)=x ¹⁵ +x ¹³ +x ⁹ +x ⁸ +x ⁷ +x ⁵+1P _(Q)(x)=x ¹⁵ +x ¹² +x ¹¹ +x ¹⁰ +x ⁶ +x ⁵ +x ⁴ +x ³+1

The output of the quadrature spreader is in the form of In-Phase (I) andQuadrature (Q) channels. The I and Q data streams (channels) are theneach passed through a Baseband Filter which shapes the waveform to meetrequired bandwidth constraints as well as minimize Inter SymbolInterference (ISI).

The I and Q channels are then modulated using Quadrature Phase Shiftkeying (QPSK). This is done in the I channel by amplitude modulating thecosine function with an amplitude of binary 0's and 1's to produce aBPSK (Binary Phase Shift Keying) waveform. In the Q channel, the sinefunction is modulated producing an orthogonal BPSK waveform. Thesummation of the BPSK waveforms then yields the QPSK waveform.

To the applicant's knowledge all existing CDMA systems are implementedas hardware. Recently, it has been proposed that existing cellulartelecommunications hardware could be replaced by a software implementedradio telecommunication system. It will be appreciated thatsoftware-implementations will benefit from an efficient technique forupdating the registers holding the long and short codes.

SUMMARY OF THE INVENTION

Accordingly, the invention provides a method of updating a pseudo noisecode shift register from a current value to a new value, including:

-   a) representing a tap polynomial as a tap polynomial binary    sequence;-   b) logically AND-ing the value of a last stage of the current value    of the register with each of the bits of the tap polynomial    sequence; and-   c) logically XOR-ing the r sult of step b) with the current value of    the register.

Preferably, step (b) is performed by extending said value of a laststage of said register to at least a sequence length of said tappolynomial binary sequence and logically AND-ing said sign extendedvalue with said tap polynomial binary sequence.

In one embodiment, the method involves the steps of shifting the currentvalue of the register one bit towards the most significant bit andassigning the value of the last stage of the current value of theregister to the first stage of the new value of the register after step(c).

In another embodiment, the invention representing the tap polynomialinvolves producing a binary sequence which is shifted by one bit towardsthe most significant bit, with the least significant bit set to 1, andthe method involves shifting the current value of the register by onebit towards the most significant bit before performing step (b).

BRIEF DESCRIPTION OF THE DRAWINGS

An example of a preferred embodiment of the invention will now bedescribed in relation to the accompanying drawings in which:

FIGS. 1A, 1B and 1C, illustrate the forward CDMA channel structure;

FIG. 2 is a flow chart showing the method of a first embodiment of theinvention; and

FIG. 3 is a flow chart showing the method of a second embodiment of theinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In a CDMA system the link between a mobile station and a base station ismade up of two channels, the forward channel (from the base station tothe mobile station) and the reverse channel (from the mobile station tothe base station).

The preferred embodiment relates to the transmit section of the forwardchannel. A description of a forward CDMA channel will now be given.

FIGS. 1A, 1B and 1C illustrate the forward CDMA channel structure of theprior art. The preferred embodiment relates to a modification of thisforward channel structure as it specifically relates to a method whichallows quadrature spreading to be efficiently performed in software.

As FIGS. 1A-1C show, the forward channel is composed of four differenttypes of code channels: a pilot channel 20 a, sync channel 20 b, pagingchannels 20 c and forward traffic channels 20 d.

A typical forward CDMA channel consists of 64 code channels that areavailable for use. The 64 code channels are comprised of a pilotchannel, a sync channel, seven paging channels and fifty-five forwardtraffic channels.

The pilot channel 20 a is an unmodulated, direct-sequence spreadspectrum signal that is transmitted at all times by the base station onevery active forward channel. The mobile station monitors the pilotchannel to acquire the timing of the forward CDMA channel and provides aphase reference for coherent demodulation.

The sync channel 20 b is used to transport synchronization messages tomobile stations within the CDMA cell. It is used by the mobile stationto acquire initial time synchronization.

The paging channels 20 c are used to transmit control information andpages to mobile stations residing in the CDMA cell.

The forward traffic channels 20 d are used for transmission of user andsignaling traffic from the base station to a specific mobile stationduring a phone call.

Referring to FIGS. 1A and 1B, all of the code channels 20 a-20 d in theforward CDMA channel are orthogonally spread by the appropriate Walshfunction 36 before they undergo quadrature spreading. However, as knownto persons skilled in the art, the sync channel, paging channel andforward traffic channel undergo several other processes which will nowbe described.

The sync, paging and traffic channels all undergo convolutional encodingusing a convolutional encoder 101, 201, 303. This process protects thesystem from errors that can occur at the high data rates used in CDMA.In convolutional encoding, the channel data streams are divided intosmaller blocks of length k and are then encoded into code word symbolsof length n. The (n, k, m) convolutional code is implemented where k isthe input, n is the output and m is memory order. The rate of theencoder is then defined by the code rate R=k/n. The sync, paging andtraffic channels all use an encoder with a code rate R=1/2.

Symbol repetition 102, 202, 304 is also used by all channels except thpilot channel. The function of this process is to increase the data rateto the level used by the Block Interleaver 103, 203, 305, which is 19200sps (symbols per second) or 19.2 ksps. For example, the data rate on thesync channel aft r convolutional encoding is 2.4 ksps. This value isincreased 8 times to 19.2 Ksps by repeating each convolutionally encodedsymbol 7 times. A 9.6 ksps stream however (such as the one in the pagingchannel), would only need to be repeated once to produce a 10.2 kspsstream.

Block interleaving 103, 203 and 305 is performed in order to reorder asequence of symbols and is performed to achieve time diversity andimprove performance.

Long code generation is performed in the paging and traffic channels bylong code generator 204, 307. The Long Code Generator produces longcodes, which are 42 bit pseudo-noise PN sequences that are used forscrambling on the forward CDMA channel which produces limited privacy.

The Long Code Generator produces 2⁴²−1 combinations of different longcode and each long code uniquely identifies a mobile station on both theforward traffic channel and reverse traffic channel. The long code ischaracterized by the long code mask that is used to form either thepublic long code or the private long code. The long code is specified bythe characteristic polynomialp(x)=x⁴²+x³⁵+x³³+x³¹+x²⁷+x²⁶+x²⁵+x²²+x²¹+x¹⁹+x¹⁸+x¹⁷+x¹⁶+x¹⁰+x⁷+x⁶+x⁵+x³+x²+x¹+1.

The output of the Long Code Generator is fed through a Decimator 205,309. The Decimator reduces the size of the long code by taking 1 out ofevery 64 bits. This has the result of reducing the data rate from1228800 cps (chips per second) or 1.2288 Mcps to 19.2 ksps.

As mentioned above, after the above-described processes have beenperformed on the relevant channels, all the code channels on the forwardCDMA channel are orthogonally spread using Walsh Functions at a fixedchip rate of 1.2288 Mcps. This provides orthogonal channelization amongall code channels. The pilot channel is always spread with Walsh code 0,the SYNC channel is always spread with Walsh channel 32 and the pagingchannels are assigned code channels 1 through 7.

As shown in FIG. 1C, following Walsh spreading, all code channelsundergo quadrature spreading, which involves performing the modulo-2addition of the orthogonally spread data of each code channel with a PNshort code sequence generated by the short code generator. The tappolynomials for the Short Code shift registers are:P _(I)(x)=x ¹⁵ +x ¹³ +x ⁹ +x ⁸ +x ⁷ +x ⁵+1P _(Q)(x)=x ¹⁵ +x ¹² +x ¹¹ +x ¹⁰ +x ⁶ +x ⁵ +x ⁴ +x ³+1The output of the quadrature spreader is in the form of In-Phase (I) andQuadrature (Q) channels 401, 402. It is possible that alternativetechniques may be used for quadrature spreading. However, irrespectiveof the technique used, the spread data will be combined with the shortcode.

The I and Q data streams (channels) are then each passed through aBaseband Filter 403 which shapes the waveform to meet required bandwidthconstraints as well as minimize y(ISI).

After the required filtering, the I and Q channels are modulated usingQuadrature Phase Shift keying (QPSK). This is done in the I channel byamplitude modulating the cosine function with an amplitude of binary 0'sand 1's to produce a BPSK (Binary Phase Shift Keying) waveform. In the Qchannel, the sine function is modulated producing an orthogonal BPSKwaveform. The summation of the BPSK waveforms then yields the QPSKwaveform which is transmitted on the forward channel.

It will be apparent that each of the long and short codes must bemaintained in a shift register which needs to be updated after each chipof code is generated.

The techniques of the preferred embodiment will now be describedgenerically in relation to FIGS. 2 and 3. Following the genericdescription, there are specific examples of how the techniques can beapplied to updating shift registers for both long and short codes.

FIG. 2 shows the technique of the preferred embodiment.

It will be appreciated that the tap polynomial for either the long orshort code can be represented as a binary sequence. This needs to becombined with the current value of the shift register in order to obtainthe new value of the shift register.

In the first preferred embodiment, the tap polynomial binary sequence isshifted one bit towards the most significant bit and the leastsignificant bit is set to have the value 1. This produces a shifted tappolynomial constant which is stored in a data entity as indicated bystep 14. The method then involves getting initial or current value ofthe shift register at step 10 and extending the last bit of the shiftregister to have sufficient bits in order for it to be combined with theshifted tap polynomial constant. At step 16 an AND operation isperformed on the shifted tap polynomial constant using the sign extendedlast bit of the shift register. At step 18 the current value of theshift register is shifted by one bit towards the most significant bit.This shifted register is then combined at step 19 with the result of theAND operation performed at step 16 by performing an XOR operation. Theresult of the XOR operation then implicitly provides the new value ofthe shift register which can then be used to generate a further bit oflong or short code.

FIG. 2 shows a slightly less efficient technique of a second lesspreferred embodiment. In this embodiment an unshifted tap polynomialconstant is used as indicated at step 35. At step 30 the initial valueof the shift register is obtained and the last bit of the shift registeris sign extended. At the same time, the value of the last bit is savedat step 32. The sign extended last bit of the shift register is combinedwith the tap polynomial constant at step 38 using an AND operation andthe result of this AND operation is combined with the initial value ofthe shift register using XOR operation at step 40. Following the XORoperation the result of the XOR operation is shifted towards the mostsignificant bit and the saved value of the last bit from step 32 isloaded into the least significant bit at step 44 to produce the newvalue of the register at step 46.

EXAMPLE 1 Long Code

Following, the calculation of a chip of long code it is necessary toquickly update the shift register so that the next chip can begenerated.

The Binary sequence that represents the long code tap polynomialp(x)=x⁴²+x³⁵+x³³+x³¹+x²⁷+x²⁶+x²⁵+x²²+x²¹+x¹⁹+x¹⁸+x¹⁷+x¹⁶+x¹⁰+x⁷+x⁶+x⁵+x³+x²+x¹⁺1is given by

-   100000010101000111001101111000001001110111    with the MSB is on the left and the LSB is on the right.

Shifting the register prior to applying the tap polynomial provides themost efficient technique for updating the shift register holding thelong code. Bit O of the shifted version of tap polynomial is assignedthe value 1. The shifted tap polynomial has the following form:

-   000000101010001110011011110000010011101111

The value of the last stage of the shift-register is saved and signextended to have the same number of bits as the long code tap polynomialas indicated by step 12 of FIG. 2. Then an AND operation is performedwith the shifted tap polynomial. The first stage of the register will beloaded with the desired value automatically without any explicitoperation.

Assume that 42-bit data is representing the current state of the longcode sequence stored in two 32-bit data entities, and is for example:

Bit 31 Bit 0  0110 1110 1010 0000 0100 0111 0110 0101  Bit 63 Bit 32 0000 0000 0000 0000 0000 0011 0001 1101  Note that bits 42-63 areallocated the value 0.

The fast shift register update is then carried out as follows:

The shifted version of the tap polynomial is stored in two 32-bitentities as:

Bit 31 Bit 0  1000 1110 0110 1111 0000 0100 1110 1111  Bit 63 Bit 32 0000 0000 0000 0000 0000 0000 0000 1010 

This represents the actual polynomial for CDMA systems shifted by onebit with Bit 0 set to 1.

Last stage of the shift register (Bit 41) is 1. Sign extending it to32-bits gives:

-   1111 1111 1111 1111 1111 1111 1111 1111

This is saved. If a 64-bit data entity were used, the last stage wouldneed to be sign extended to 64-bits. That is, in the 32-bit case thedata entity holding the extended last stage can be used to perform theAND operation on both the entities in which the polynomial is stored.

Now we shift the shift register left by one bit.

Result is:

Bit 31 Bit 0  1101 1101 0100 0000 1000 1110 1100 1010  Bit 63 Bit 32 0000 0000 0000 0000 0000 0010 0011 1000  Note that as we arerepresenting a 42-bit register, bits 42 to 63 are always assigned thevalue “0”.

Logically AND-ing both 32-bit entities of polynomial with the savedvalue of the sign-extended last stage gives the polynomial result:

Bit 31 Bit 0  1000 1110 0110 1111 0000 0100 1110 1111  Bit 63 Bit 32 0000 0000 0000 0000 0000 0000 0000 1010 

Logically XOR-ing those values with the shifted shift register producesthe result:

-   1101 1101 0100 0000 1000 1110 1100 1010 XOR (Shift Register value    bits 0-31)-   1000 1110 0110 1111 0000 0100 1110 1111 (Polynomial result bits    0-31)    Results:

Bit 31 Bit 0  0101 0011 0010 1111 1000 1010 0010 0101  (New value ofshift register, bits 0-31) 0000 0000 0000 0000 0000 0010 0011 1000  XOR(Shift Register value bits 32-63) 0000 0000 0000 0000 0000 0000 00001010  (Polynomial bits 32-63)Equal to:

Bit 63 Bit 32  0000 0000 0000 0000 0000 0010 0011 0010  (New value ofshift register, bits 32-63)New value of shift register is:

Bit 31 Bit 0  0101 0011 0010 1111 1000 1010 0010 0101  Bit 63 Bit 32 0000 0000 0000 0000 0000 0010 0011 0010 

In the second preferred embodiment all stages of the shift register thatcorrespond to a polynomial tap are XOR-ed with the value of the laststage, the shift register is then shifted and the value of the laststage is fed into the first stage of the shift register. The desiredeffect is obtained by converting the tap polynomial into a 42-bit binarysequence, then AND-ing every bit of it with the output from last stageof the shift register, and finally XOR-ing the result with current stateof the shift register. Once this operation is complete, the contents ofthe entire shift register are shifted once and the saved value of thelast stage is moved into the first stage.

EXAMPLE 2 Short Code

The shifting of the short code register occurs 1536 times for everypower control group (PCG), with both the I and Q shift registersrequiring this operation. The tap polynomials for the Short Code shiftregisters are:P _(I)(x)=x ¹⁵ +x ¹³ +x ⁹ +x ⁸ +x ⁷ +x ⁵+1P _(Q)(x)=x ¹⁵ +x ¹² +x ¹¹ +x ¹⁰ +x ⁶ +x ⁵ +x ⁴ +x ³+1

The shift registers for the I and the Q branches are represented by16-bit data entities. Thus, both shift registers will occupy only 32bits of memory.

The register is shifted prior to applying the tap polynomial. The tappolynomial is also shifted with the first bit set to 1. The shifted tappolynomials have the following forms:

-   0010 0011 1010 0001 (I-sequence, listed from left to right in the    order MSB to LSB)-   0001 1100 0111 1001 (Q-sequence, listed from left to right in the    order MSB to LSB)    It will be noted that bit 15 has been set to zero.

The shifted tap polynomials are then logically AND-ed with the extendedvalue of the last stage of the shift register before the result islogically XOR-ed with the shifted shift register.

In the alternative, the tap polynomial is converted into a 15-bit binarysequence. This sequence is logically AND-ed with the output from thelast stage of the register and XOR the result with current value ofshift register. After that shift register is shifted one bit towards themost significant bit and the value of the last stage is fed into thefirst stage.

In this case the unshifted binary sequences that represent the tappolynomials are:

-   0101 0001 1101 0000 (I-sequence, listed from left to right in the    order MSB to LSB)-   0100 1110 0011 1100 (Q-sequence, listed from left to right in the    order MSB to LSB)    It will be noted that bit 15 has been set to zero.

Instead of AND-ing every bit of the tap polynomial sequence with thevalue of the last stage of the register (which requires 15 shifts and 15AND operations), the value of the last shift register stage is firstextended to the full 15 bits (actually to 16 bits in a C languageimplementation, where the shift register is physically represented by a16 bit data entity). We then make use of signed arithmetic and shiftthis value left to the MSB position and shift it back to the LSBposition to sign extend the value to the full 16 bits.

The value of the last stage is saved and sign-extended to 16-bits. TheAND and XOR operation can now be accomplished easily and the register isshifted one bit towards the most significant bit. Finally the previousvalue of the last stage of shift register is assigned to the firststage.

It will also be apparent that skilled programmers can generate anappropriate computer program for implementing the method of theinvention. The invention includes within its scope such a program and aprocessor, such as a DSP, so programmed.

Various modifications to the foregoing system will be apparent topersons skilled in the art and should be considered as falling withinthe scope of the present invention.

1. A method of updating a pseudo noise code shift register of asoftware-implemented radio telecommunication system from a current valueto a new value, including: a) representing a tap polynomial as a tappolynomial binary sequence; b) logically AND-ing the value of a laststage of the current value of the register with each of the bits of thetap polynomial sequence; c) logically XOR-ing the result of step b) withthe current value of the register; and d) updating the pseudo noise codeshift register according to step c), wherein representing the tappolynomial involves producing a binary sequence which is shifted by onebit towards the most significant bit, with the least significant bit setto 1, and the method involves shifting the current value of the registerby one bit towards the most significant bit before performing step (b).2. A method as claimed in claim 1, wherein step (b) is performed byextending said value of a last stage of said register to at least asequence length of said tap polynomial binary sequence and logicallyAND-ing said sign extended value with said tap polynomial binarysequence.
 3. A method as claimed in claim 1, wherein the method involvesthe steps of shifting the current value of the register one bit towardsthe most significant bit and assigning the value of the last stage ofthe current value of the register to the first stage of the new value ofthe register after step (c).
 4. A method as claimed in claim 1, whereinthe sequence length is 42-bits.
 5. A method as claimed in claim 1,wherein the sequence length is 15-bits.
 6. A method as claimed in claim1, wherein a computer processor is used to carry out step (a), step (b),step (c) and step (d).
 7. A method as claimed in claim 6, wherein saidprocessor is a digital signal processor.
 8. A computer program forupdating a pseudo noise code shift register of a software-implementedradio telecommunication system from a current value to a new value, thecomputer program recorded on a computer-readable medium and comprising:a) code for representing a tap polynomial as a tap polynomial binarysequence; b) code for logically AND-ing the value of a last stage of thecurrent value of the register with each of the bits of the tappolynomial sequence to form an intermediate value; c) code for logicallyXOR-ing the intermediate value with the current value of the register;and d) updating the pseudo code shift register according to step c)wherein representing the tap polynomial involves producing a binarysequence which is shifted by one bit towards the most significant bit,with the least significant bit set to 1, whereby the current value ofthe register is shifted by one bit towards the most significant bitbefore logically AND-ing the value of the last stage of said registerwith each of the bits of said tap polynomial sequence to form saidintermediate value.
 9. The computer program of claim 8, wherein saidvalue of a last stage of said register is extended to at least asequence length of said tap polynomial binary sequence.